Array operation using a schottky diode as a non-ohmic selection device

ABSTRACT

A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

RELATED APPLICATIONS

This application is a continuation of and claims priority to pendingU.S. patent application Ser. No. 13/555,873, filed Jul. 23, 2012, whichis a continuation of and claims priority to U.S. patent application Ser.No. 13/246,654, filed Sep. 27, 2011, now issued as U.S. Pat. No.8,254,196, which is a continuation of and claims priority to U.S. patentapplication Ser. No. 12/584,262, filed Sep. 2, 2009, now issued as U.S.Pat. No. 8,027,215, which is a non-provisional of and claims priority toU.S. Provisional Patent Application No. 61/203,189, filed Dec. 19, 2008,to U.S. Provisional Patent Application No. 61/203,163, filed Dec. 19,2008, to U.S. Provisional Patent Application No. 61/203,160, filed onDec. 19, 2008, to U.S. Provisional Patent Application No. 61/203,184,filed on Dec. 19, 2008, to U.S. Provisional Patent Application No.61/203,187, filed on Dec. 19, 2008, and to U.S. Provisional PatentApplication No. 61/203,192, filed on Dec. 19, 2008, all of which areincorporated herein by reference and in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductors and memorytechnology. More specifically, the present invention relates to a memorycell including a non-ohmic isolation device.

BACKGROUND OF THE INVENTION

Large arrays of two-terminal memory cells can require an isolationdevice (non-ohmic device—NOD) in order to avoid having substantialcurrent flow through unselected or half-selected memory cells.Conventional approaches include using a metal-insulator-metal (MIM)diode as a device through which current can flow in either polarity ofapplied voltages during data operations (e.g., read and writeoperations) to a selected memory cell. However, in some configurations,the MIM diode can exhibit a sufficiently high “half-select” leakageratio, that is, some current continues to flow through half-selectedmemory cells.

It is desirable to eliminate leakage currents associated withhalf-selected and un-selected memory cells during data operations,especially during read operations where the leakage currents can reducethe ability of sense circuitry to accurately sense a read currentgenerated by one or more selected memory cells. Leakage currents canreduce a signal to noise ratio (S/N) resulting in read errors.Therefore, a high the S/N ratio is desirable and reducing or eliminatingleakage currents can improve the S/N ratio. Furthermore, a high S/Nratio can reduce the complexity and size of the sense amp circuitry usedfor reading data from memory cells during read operations.

Reference is now made to FIG. 1A, where a schematic of a conventionalmemory array 150 includes a plurality of memory cells 100 arranged in across-point configuration with each cell 100 including a conventionalMIM diode 106 electrically in series with a memory element 121, a firstterminal 102, and a second terminal 104. The first terminal 102 iselectrically coupled with a conductive array line 112 (e.g., a columnline) and the second terminal 104 is electrically coupled with aconductive array line 110 (e.g., a row line). The conventional MIM diode106 comprises a conventional non-ohmic isolation device. The array 150depicts three row conductive array lines denoted as row-1, row-2, androw-3, and three column conductive array lines denoted as col-1, col-2,and col-3. The array 150 can include fewer or more conductive arraylines and memory cells 100 than depicted in FIGS. 1A and 1B.

In FIG. 1A, voltage potentials for a data operation (e.g., a read orwrite operation) are applied to the row-2 and col-2 conductive arraylines (depicted in heavy line) to select a specific memory cell 100′ inthe array 150 for the data operation. Here the data operation is a writeoperation to program the selected memory cell 100′ (e.g., a programmingoperation). A voltage potential +V1 is applied to conductive array linerow-2 and a voltage potential −V1 is applied to conductive array linecol-2 such that the potential difference across the selected memory cell100′ is: +V1−(−V1)=+2V1. A potential of 0V is applied to all remainingconductive array lines. Accordingly, a table 170 depicts the potentialdifference across the memory cells 100 in the array 150. Memory cells100 having only one of their two terminals (102 or 104) electricallycoupled with the row-2 or col-2 conductive array lines are half-selectedmemory cells 100 because they have one terminal at 0V and other terminalat +V1 or −V1. Therefore, the potential difference across those memorycells 100 is +V1 (e.g., +V1−0V or 0V−(−V1)). Similarly, memory cells 100having both terminals (102 and 104) electrically coupled with conductivearray lines at the 0V potential are un-selected memory cells 100 with apotential difference across those memory cells 100 being approximately0V.

Turning now to FIG. 1B, the array 150 is schematically depicted duringan erase operation to the same selected memory cell 100′. Here, thepolarity of the applied voltages on conductive array lines row-2 andcol-2 is the opposite of that depicted in FIG. 1A such that the voltageapplied to row-2 is −V1 and the voltage applied to col-2 is +V1resulting in a potential difference across the selected memory cell 100′of: −V1−(+V1)=−2V1. A table 190 depicts the potential difference acrossall the memory cells 100 in the array 150 with un-selected memory cells100 having a potential difference of approximately 0V and half-selectedmemory cells 100 having a potential difference of −V1.

Moving now to FIG. 2, an I-V curve for the memory cells 100 with theconventional MIM diode non-ohmic isolation device 106 depicts currentflow I (on the y-axis) through a memory cell 100 as a function of thevoltage V (on the x-axis) applied across the memory cell 100. Forprogram and erase operations on the memory cell 100 (e.g., selectedmemory cell 100′), the magnitude of the current I is highest atoperating point 212 for the applied voltage of +2V1 and operating point214 for the applied voltage −2V1. The magnitude of current I is expectedat those levels of applied voltage for a selected memory cell 100′because that cell is being programmed or erased. However, forhalf-selected and un-selected memory cells, some current I still flowsas depicted at operating points 215 and 217 for applied voltages of +V1and −V1, respectively. Although operating points 215 and 217 aredepicted at +V1 and −V1, moving along the voltage axis from −V1 to 0V or+V1 to 0V, some current I still flows through memory cells 100. Forexample, if the applied voltage across un-selected memory cells 100 isnot exactly 0V, then a voltage potential exists across those memorycells 100 and some leakage current can flow through those cells.

Although the FIGS. 1A through 2 depict applied voltages for program anderase operations, for read operations where the magnitude of the voltageapplied across the selected memory cell 100′ is typically less than thatapplied for program and erase operations, there will still beun-selected and half-selected memory cells in the array 150 having apotential difference across their terminals (102, 104) that can generateleakage currents that lower the aforementioned S/N ratio during readoperations. Ideally, a non-ohmic device would allow current to flow onlythrough selected memory cells 100′ and would block current flow throughhalf-selected and un-selected memory cells 100. Preferably, theoperating points for half-selected and un-selected memory cells 100would be on the voltage axis V where the current I is 0 A.

There are continuing efforts to improve selection devices fornon-volatile memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Various examples are disclosed in the following detailed description andthe accompanying drawings.

FIG. 1A depicts a schematic view of a conventional memory array during aprogramming operation to a memory cell including a conventional MIMdiode NOD;

FIG. 1B depicts a schematic view of a conventional memory array duringan erase operation to a memory cell including a conventional MIM diodeNOD;

FIG. 2 depicts an I-V curve for a memory cell including a conventionalMIM diode NOD;

FIG. 3A depicts a schematic view of a memory array during a programmingoperation to a memory cell including a single Schottky diode NODisolation device according to the present invention;

FIG. 3B depicts a schematic view of a memory array during a sector eraseoperation to memory cells including a single Schottky diode NODisolation devices according to the present invention;

FIG. 3C depicts a schematic view of a memory array during a readoperation to a memory cell including a single Schottky diode NODisolation device according to the present invention;

FIG. 4 depicts an I-V curve for a memory cell including a singleSchottky diode NOD isolation device according to the present invention;

FIG. 5 depicts a cross-sectional view of a single Schottky diode NODisolation device integrated with a memory element in a memory cellaccording to the present invention;

FIG. 5A depicts a cross-sectional view of one example of a singleSchottky diode NOD isolation device integrated with a memory element ina memory cell according to the present invention;

FIGS. 6A-6D depict a cross-sectional views of alternate embodiments ofan oxide semiconductor based single Schottky diode NOD isolation deviceintegrated with a memory element in a memory cell according to thepresent invention;

FIG. 7A depicts an example of memory cells positioned in a two-terminalcross-point array according to various embodiments of the invention;

FIG. 7B depicts a single layer or multiple vertically stacked layers ofmemory arrays formed BEOL on top of a base layer including circuitryformed FEOL;

FIG. 7C depicts one example of a vertically stacked memory includingmultiple array layers that share conductive array lines and formed BEOLon top of a previously formed FEOL base layer;

FIG. 8A depicts a cross-sectional view of an integrated circuit dieincluding a single layer of memory fabricated over a substrate includingactive circuitry fabricated in a logic layer;

FIG. 8B depicts a cross-sectional view of an integrated circuit dieincluding vertically stacked layers of memory fabricated over asubstrate including active circuitry fabricated in a logic layer;

FIG. 8C depicts an integrated circuit die including vertically stackedlayers of memory with shared conductive array lines fabricated over asubstrate including active circuitry fabricated in a logic layer;

FIG. 9 depicts a memory system including a non-volatile two-terminalcross-point array;

FIG. 10 depicts an exemplary electrical system that includes at leastone non-volatile two-terminal cross-point array; and

FIG. 11 depicts top plan views of a wafer processed FEOL to form aplurality of base layer die including active circuitry and the samewafer subsequently processed BEOL to form one or more layers of memorydirectly on top of the base layer die where the finished die cansubsequently be singulated, tested, and packed into integrated circuits.

Although the previous drawings depict various examples of the invention,the invention is not limited by the depicted examples. It is to beunderstood that, in the drawings, like reference numerals designate likestructural elements. Also, it is understood that the depictions in theFIGS. are not necessarily to scale.

DETAILED DESCRIPTION

Various embodiments or examples may be implemented in numerous ways,including as a system, a process, an apparatus, or a series of programinstructions on a computer readable medium such as a computer readablestorage medium or a computer network where the program instructions aresent over optical, electronic, or wireless communication links. Ingeneral, operations of disclosed processes may be performed in anarbitrary order, unless otherwise provided in the claims.

A detailed description of one or more examples is provided below alongwith accompanying figures. The detailed description is provided inconnection with such examples, but is not limited to any particularexample. The scope is limited only by the claims, and numerousalternatives, modifications, and equivalents are encompassed. Numerousspecific details are set forth in the following description in order toprovide a thorough understanding. These details are provided as examplesand the described techniques may be practiced according to the claimswithout some or all of the accompanying details. For clarity, technicalmaterial that is known in the technical fields related to the exampleshas not been described in detail to avoid unnecessarily obscuring thedescription.

U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005,entitled “Memory Using Mixed Valence Conductive Oxides,” and publishedas U.S. Pub. No. US 2006/0171200 A1 on Aug. 3, 2006, is hereinincorporated by reference in its entirety and for all purposes anddescribes non-volatile third dimensional memory elements that may bearranged in a two-terminal, cross-point memory array. The memoryelements can be a component of a memory cell that includes electricallyin series with the memory element, other structures including but notlimited to a non-ohmic device (NOD) and electrodes. New non-volatilememory structures are possible with the capability of this thirddimensional memory array. The technology allows for the emulation ofother memory technologies by duplicating the interface signals andprotocols, while accessing the third dimensional memory array. The thirddimensional memory array may emulate other types of memory (e.g., DRAM,SRAM, FLASH, and ROM), providing memory combinations (e.g., DRAM, FLASH,and SRAM) within a single component. In at least some embodiments, atwo-terminal memory cell can be configured to change conductivity whenexposed to an appropriate voltage drop across the two-terminals. Thememory cell can include an electrolytic tunnel barrier and a mixedvalence conductive oxide (e.g., a memory element) in some embodiments,as well as multiple mixed valence conductive oxide structures in otherembodiments. A voltage drop across the electrolytic tunnel barrier cancause an electrical field within the mixed valence conductive oxide thatis strong enough to move oxygen ions out of the mixed valence conductiveoxide, according to some embodiments.

In some embodiments, an electrolytic tunnel barrier and one or moremixed valence conductive oxide structures do not need to operate in asilicon substrate, and, therefore, can be fabricated (e.g.,back-end-of-the-line BEOL) above circuitry being used for other purposes(e.g., circuitry fabricated front-end-of-the-line FEOL). The circuitryportion of an IC can be fabricated FEOL on a substrate (e.g., a siliconSi wafer) that is partitioned into die with each die forming the basestructure for the IC. After the FEOL processing is completed thesubstrate is processed BEOL to fabricate the one or more layers ofmemory directly on top of each FEOL die. An inter-level interconnectstructure formed FEOL serves as the structural and electrical foundationfor the subsequent formation of the one or more layers of memory thatwill be deposited (e.g., formed) on top of the FEOL die. The inter-levelinterconnect structure includes vias, plugs, damascene structures or thelike, that allow the FEOL circuitry to be electrically coupled with theBEOL memory layer(s). After BEOL processing is completed, the finisheddie can be singulated from the substrate (e.g., removed by sawing orcutting) to form individual die that can be inserted into a suitablepackage and electrically coupled with bonding pads or other structuresin the package to form an integrated circuit (IC). Therefore, each dieis an integral unit that includes at a bottommost layer the FEOLcircuitry and upper layers comprised of one or more layers of thirddimensional memory that are positioned above the FEOL circuitry layer.Unlike conventional IC's that have conventional memory (e.g., SRAM,DRAM, and FLASH) fabricated FEOL on the same substrate die as thecircuitry that accesses the memory such that the memory and thecircuitry are disposed on the same physical plane, the BEOL thirddimensional memory layer(s) are not on the same plane as the FEOLcircuitry and therefore do not take up area on the FEOL die.Accordingly, data storage can be increased without increasing the areaof the FEOL die by fabricating additional BEOL memory layers on top ofthe FEOL die (e.g., along the +Z axis of FIGS. 7B-8C).

Further, a two-terminal memory cell can be arranged in a cross-pointconfiguration such that one terminal is electrically coupled with anX-direction line (or an “X-line”) and the other terminal is electricallycoupled with a Y-direction line (or a “Y-line”). A third dimensionalmemory can include multiple memory cells vertically stacked upon oneanother, sometimes sharing X-direction and Y-direction lines in a layerof memory, and sometimes having electrically isolated X and Y directionlines (e.g., using a dielectric material such as SiO₂). When a firstwrite voltage, VW1, is applied across the memory cell (e.g., by applying½ VW1 to the X-direction line and ½−VW1 to the Y-direction line), thememory cell can switch to a low resistive state. When a second writevoltage, VW2, is applied across the memory cell (e.g., by applying ½ VW2to the X-direction line and ½−VW2 to the Y-direction line), the memorycell can switch to a high resistive state. Memory cells usingelectrolytic tunnel barriers and mixed valence conductive oxides canhave VW1 opposite in polarity from VW2.

Attention is now directed to FIG. 3A where a schematic of a memory array350 is depicted. The array 350 is a 3×3 array with three row conductorsdenoted as row-1, row-2, and row-3 and three columns conductors denotedas col-1, col-2, and col-3; however, the array 350 can be any size andis not limited to the 3×3 array depicted in FIG. 3A. The array 350 caninclude a plurality of two-terminal memory cells 300 positioned in across-point array configuration with each memory cell 300 including afirst terminal 304 electrically coupled with one of the row conductorsand a second terminal 306 electrically coupled with one of the columnconductors. Each memory cell 300 further includes a two-terminal memoryelement 302 and a single Schottky diode 321 non-ohmic isolation device(NOD) that are electrically in series with each other and electricallyin series with the terminals 304 and 306.

Data operations (e.g., read and write operations) on the memory cells300 require appropriate voltage potentials be applied to selectedconductive array lines. In FIG. 3A a write operation (e.g., aprogramming operation) to the memory cell 300 in (row-2, col-2) isaccomplished by applying a voltage potential of +V1 to conductor row-2and a voltage potential −V1 to conductor col-2 to select the memory cell300 for a programming operation. The selected memory cell is denoted as300′. The remaining row conductors have voltage potential of −V1 appliedto them and the remaining column conductors have a voltage potential of+V1 applied to them. A programming table 370 depicts the voltage acrossthe selected memory cell 300′ and across un-selected memory cells 300.In table 370, the selected memory cell 300′ has a potential differenceof +2V1 across its terminals (304, 306) and un-selected memory cells 300have a 0V or a −2V1 potential difference across their terminals (304,306). The applied voltages can be shifted up or down relative to what isdepicted in FIG. 3A and are not limited to the +V1 and −V1 shown. Here,the terminology un-selected memory cell 300 means any memory cell 300that is not the selected memory cell 300′ even though some of the memorycells 300 can be designated as half-selected memory cells 300. Toclarify the status of the cells 300 in the array 350 using standardparlance, in the programming operation in FIG. 3A, cells 300 denoted asHS are half-selected memory cells and cells 300 denoted as US areun-selected memory cells.

The asymmetrical characteristics of the single Schottky diode 321 and621 (see 621 in FIGS. 6A-6D) allow tolerable levels of unselected cell300 leakage in the array 350 (e.g., approximately a 4000:1 current ratiobetween the selected device 300′ and an unselected devices 300 with thesame voltage at reverse polarity). Essentially, the reverse leakagecharacteristics of the single Schottky diode 321 are expected to bebetter than the half-selected leakage characteristics of theconventional MIM diode 106 described above in reference to FIGS. 1A-2.

Unlike the conventional MIM device 106 described above in reference toFIGS. 1A and 1B, the Schottky diode (321, 621) is not subject todielectric breakdown failure mechanisms such as time-dependentdielectric breakdown or stress-induced leakage current. The current andtotal fluence (C/cm²) that may be passed through the single Schottkydiode (321, 621) before failure is much higher than that of theconventional MIM diode 106. The single Schottky diode (321, 621) has awell-controlled reverse breakdown voltage; sector erase is possible bybiasing the diodes (321, 621) on multiple cells 300 into reversebreakdown.

Reference is now made to FIG. 3B where a schematic depicts a sectorerase operation (also referred to as a block erase operation) to thearray 350. Here, all the row conductors 310 have an applied voltagepotential of −V2 and all the column conductors 312 have an appliedvoltage potential of +V2. Consequently, all the memory cells areselected for the erase operation and are denoted as selected memorycells 300′. In an erase table 380, the potential difference across theterminals (304, 306) of selected memory cells 300′ is −2V2, that is:−V2−(+V2)=−2V2.

Variations on the erase operation of FIG. 3B can include erasing thememory cells 300′ in a selected column of the array 350 or in a selectedrow of the array 350. As one example of how the memory cells 300′ in aselected column can be erased, column conductors col-1 and col-2 canhave a voltage potential of approximately 0V applied to them, col-3 canhave a voltage potential of +V2 applied to it, and row conductors row-1,row-2, and row-3 can have a voltage potential of −V2 applied to them.Consequently, all of the memory cells 300 in col-1 and col-2 arehalf-selected during the erase operation with a potential difference of−V2 (e.g., −V2−0V) across their terminals and in col-3 all of the memorycells 300′ are selected for the erase operation and have a potentialdifference of −2V2 (e.g., −V2−(+V2)) across their terminals.

As another example of how all the memory cells 300′ in a selected rowcan be erased, row conductors row-1 and row-3 can have a voltagepotential of approximately 0V applied to them, row-2 can have a voltagepotential of −V2 applied to it, and column conductors col-1, col-2, andcol-3 can have a voltage potential of +V2 applied to them. Consequently,all of the memory cells 300 in row-1 and row-3 are half-selected duringthe erase operation with a potential difference of +V2 (e.g., 0V−(−V2))across their terminals and in row-2 all of the memory cells 300′ areselected for the erase operation and have a potential difference of −2V2(e.g., −V2−(+V2)) across their terminals.

Turning to FIG. 3C, a schematic depicts a read operation performed on asingle selected memory cell 300′ in the array 350. Here, all theunselected row conductors 310 have an applied voltage potential of −V3and all un-selected column conductors 312 have an applied voltagepotential of +V3, with the selected memory cell 300′ having voltagepotentials of +V3 and −V3 applied to its row 310 and column 312conductors, respectively. A read table 390 depicts the potentialdifference across the terminals of the selected 300′ and un-selectedmemory cells 300. Un-selected memory cells 300 have a potentialdifference of −2V3 or 0V; whereas, the selected memory cell 300′ has apotential difference of +2V3. It should be noted that the magnitude ofread voltages are typically less than the magnitude of voltages forprogram or erase operations because a lower magnitude of read voltageprevents data stored in the selected memory cell(s) 300′ from beingoverwritten or corrupted during read operations. In FIG. 3C, for a readoperation |V3|<|V1| and |V3|<|V2|. For example, in FIG. 3A, if +V1=+2Vand −V1=−2V such that the potential difference across selected memorycell 300′ during the programming operation is (+2V−(−2V))=+4V, then inFIG. 3C, if +V3=+1V and −V3=−1V such that the potential differenceacross selected memory cell 300′ during the read operation is(+1V−(−1V))=+2V; therefore, |V3|<|V1| because |2V|<|4V|. The applicationof the read voltage generates a read current I_(R) that flows throughthe selected memory cell 300′ and a magnitude of the read current I_(R)is indicative of the value of stored data in the selected memory cell300′. For example, if the programmed conductivity profile comprises ahigh resistance state (e.g., programmed conductivity is low) then themagnitude of the read current I_(R) will be low when the memory cell300′ is in the programmed state. Conversely, if the erased conductivityprofile comprises a low resistance state (e.g., erased conductivity ishigh) then the magnitude of the read current I_(R) will be higher whenthe memory cell 300′ is in the erased state. Therefore, given theprevious examples, I_(R-Erased)>I_(R-Programmed). The actual conventionsfor the resistance or conductivity values for programmed and erasedstates will be application dependent and the foregoing is just oneexample of how the programmed and erased states can be defined. The readcurrent I_(R) signal along with one or more other signals (e.g., leakagecurrents and/or reference signals) can be electrically coupled withsense circuitry (e.g., FEOL active circuitry) that compares thosesignals in the current or voltage domains to generate a signal that isindicative of the valued of data stored in the selected memory cell(s)300′.

Attention is now directed to FIG. 4 where an I-V curve 400 depicts anon-linear relationship between current I on a y-axis and voltage V onan x-axis for a memory cell 300 that includes the Schottky diode NOD(321, 621). Operating points 403 and 405 for selected memory cells 300′depict current flow I through the selected memory cell(s) 300′ at apotential difference along the x-axis of +2V1 at an operating point 403and −2V2 at an operating point 405. On the other hand, an operatingpoint 404 for un-selected memory cells 300 depicts very low current flowI for a potential difference along the x-axis of −2V1 such that areverse current at −2V1 is orders of magnitude lower than a forwardcurrent at 2V1. Therefore, from about 0V on the x-axis at a point 406 toa point 408 located between voltages −2V2 and −2V1, the reverse currentfor I is substantially lower than the forward current for I from thepoint 410 to 403.

Accordingly, in FIG. 3A where un-selected memory cells 300 either have apotential difference across their terminals of 0V or −2V1, current I isvery low (e.g., at operating point 404) during the program operation toselected memory cell 300′. In FIG. 3B, since all of the memory cells areselected memory cells 300′ during the sector erase operation, all of theselected memory cells 300′ have a current I at the operating point 405at −2V2. In regard to the read operation depicted in FIG. 3C, operatingpoints 410 and 412 can depict a range of read currents I_(R) that flowwhen the read voltage +2V3 is applied across the terminals (304, 306) ofthe selected memory cell 300′. The lower value of the read current I_(R)at operating point 410 can be indicative of the memory cell 300′ storingdata in the programmed state (e.g., higher resistance=lower currentmagnitude) and the higher value of the read currents I_(R) at operatingpoint 412 can be indicative of the memory cell 300′ storing data in theerased state (e.g., lower resistance=higher current magnitude).

The Schottky diode (321, 621) may be readily integrated into a back-endprocess for fabricating BEOL memory layers. For example, amorphoussilicon may be subjected to a rapid thermal annealing step (e.g., at atemperature of about 700° C.) that converts the amorphous silicon to asingle layer of polycrystalline silicon (also called polysilicon orpoly-Si). A lightly doped n-type polysilicon line atop a metal plug onthe memory device will produce a Schottky diode. Resistivity of thepolysilicon line may be reduced by siliciding (e.g., reacting with Ni orCo) the top surface of the polysilicon to form a silicide layer (e.g.,nickel silicide or cobalt silicide). The Schottky diode (321, 621)should be easier to integrate than a p-n junction diode, in addition tohaving a better controlled reverse breakdown voltage. A silicon waferincluding active circuitry (e.g., CMOS devices) fabricated thereonduring a front-end-of-the-line process (FEOL) can include with theactive circuitry, the circuits (drivers, decoders, sense amps, buffers,registers, etc.) that interface with the BEOL array 350 for dataoperations (e.g., read, program, and erase) to the memory cells 300. TheBEOL array 350, its memory cells 300 (e.g., the two-terminal memoryelements 302 and the Schottky diodes 321 or 621), and its conductivearray lines (310, 312) can be fabricated directly on top of the siliconwafer and its active circuitry as part of a back-end-of-the-line process(BEOL). Using the BEOL process, one layer of cross-point memory array350 or multiple layers of vertically stacked cross-point memory arrays350 can be formed.

A single layer of polycrystalline silicon has advantages over using oneor more layers of amorphous silicon (also referred to as α-Si or a-Si)to form a Schottky diode. Mainly, polycrystalline silicon has a mobilityof charge carriers (e.g., in cm²/V·s) that can be orders of magnitudehigher than that of amorphous silicon. For example, if a typicalmobility of amorphous silicon is approximately less than 1 cm²/V·s, thena typical mobility of polycrystalline silicon can be approximately 10cm²/V·s or more. The higher mobility of charge carriers forpolycrystalline silicon is desirable for supporting higher current flowsthrough the memory cell 300 during data operations to the memory cells(see FIG. 4) such as read operations and write operations (e.g., programand erase operations). For read operations, a higher read current I_(R)can reduce read errors in sense amp circuitry by increasing the signalto noise ratio (S/N) such that the signal representing the read currentI_(R) in the memory cell 300′ being read is easy to distinguish overnoise signals that may be present during read operations. Furthermore,the ability of polycrystalline silicon to support higher currents can bedesirable during program and erase operations because the magnitude thevoltage applied across the memory cell 300 during write operations istypically larger than the magnitude of the read voltage, resulting inlarger magnitude currents I during write operations. Although one ormore layers of amorphous silicon such as intrinsic α-Si and/or dopedα-Si (e.g., doped n+) can be formed at lower processing temperaturesthan polycrystalline silicon, the higher processing temperaturesrequired to form the singly layer of polycrystalline silicon areworthwhile given the larger currents that can be supported by thepolycrystalline silicon.

As described above, each memory cell 300 can include two terminals (304,306) electrically coupled with their respective pair of conductive arraylines (310, 312) and the memory cell 300 can be positioned at across-point of its respective conductive array lines (310, 312). Eachmemory cell 300 can include electrically in series with its terminalsand electrically in series with each other, the memory element 302 andthe Schottky diodes (321, 621), such that the Schottky diode (321, 621)is integral with the memory cell 300.

Referring now to FIG. 5, a cross-sectional view of a structure for amemory cell 300 that includes a memory element 302 and the singleSchottky diode NOD 321 is depicted. After the memory element 302 isformed, a layer of metal 529 can be formed on top of the memory element302 followed by a deposition of a single layer of lightly dopedpolycrystalline silicon (polysilicon) 523 on top of the layer of metal529 to form the single Schottky diode NOD 321, and a silicide layer 527formed on top of the polysilicon layer 523. The single layer ofpolysilicon 523 may initially be amorphous silicon that is annealed,heated, or otherwise transformed from an amorphous silicon structure toa polycrystalline silicon structure. It may be necessary to form anohmic contact between the polysilicon layer 523 and the silicide layer527. Accordingly, a portion 525 (e.g., the portion above dashed line524) of the single layer of polysilicon 523 can be doped with a dopingtype that is opposite to the type of doping for the lightly doped layer523. For example, the polysilicon layer 523 can be lightly doped n− andthe portion 525 can be doped n+. Subsequently, a silicide layer 527 canbe deposited on the portion 525 to form the ohmic contact between layers523 and 527.

FIG. 5A depicts a cross-sectional view of one example for a structurefor the Schottky diode NOD 321 formed by contact between a layer ofmetal 529 and a single layer of n− polysilicon 523. The single layer ofn− polysilicon 523 includes a second portion comprised of n+ polysilicon525 which is in contact with a layer of a silicide material 527. Thelayer of metal 529 is positioned on top and in contact with the memoryelement 302. However, the arrangement depicted is just one example andthe layers (523, 529) need not be in direct contact with the memoryelement 302 and the memory element 302 can be positioned above the layerof metal 529 and the other layers of material for the Schottky diode NOD321. In that the memory element 302 and the NOD 321 are electrically inseries with each other, their relative positions in the memory cell 300can be determined by processing requirements and/or design requirements.Accordingly, the NOD 321 and memory element 302 need not be in contactwith each other. For example, the layer 529 in FIGS. 5 and 5A need notbe in direct physical contact with the memory element 302 and some otherelectrically conductive structure in the memory cell 300 (e.g., anelectrically conductive glue or adhesion layer) can be positionedbetween the NOD 321 and the memory element 302. Current flow through thememory cell 300 can be accomplished by placing a potential difference of−0.5V across the terminals (304, 306) of the memory cell 300 (e.g.,−0.5V on terminal 304 and 0V on terminal 306) or a potential differenceof +4V across the terminals (e.g., +4V on terminal 304 and 0V onterminal 306).

Suitable materials for the layer of silicide 527 include but are notlimited to a nickel Ni silicide and a cobalt Co silicide, for example.Suitable materials for the layer of metal 529 include but are notlimited to tungsten (W), aluminum (Al), and platinum (Pt), for example.The metal layer 529 can be a structure such as a metal plug processedusing a planarization technique such as CMP to form a substantiallyplanar upper surface upon which to deposit the single layer 523. Asingle layer of amorphous silicon Si can be deposited on the metal layer529 and surface doped (e.g., n−) using a low-energy implant or a POCl₃reaction. The single layer 523 can be subjected to rapid thermalannealing to convert the amorphous Si into polycrystalline Si and toactivate the dopant. Annealing temperatures will be applicationdependent; however, the annealing temperature can be about 700° C. orabout 500° C. or lower if metal-assisted crystallization is used.Subsequently, the single layer 523 can be patterned and etched.Additional thin film layers required by the memory cell 300 can bedeposited on the layer 523 or 527, such as a silicon nitride SiN₃ spacerlayer, for example.

FIGS. 6A through 6D depict alternate examples for the single Schottkydiode NOD 621 based on a single layer of an oxide semiconductor material611. Although the NOD 621 and memory element 302 are depicted in contactwith each other, as was described above, the NOD 621 and memory element302 need not be in contact with each other. The Schottky diode NOD 621is similar to the NOD 321 of FIGS. 5 and 5A, but the NOD 621 utilizes anoxide semiconductor in place of the lightly doped polysilicon 523 andcan use different materials for the metal electrodes. In FIG. 6A andFIG. 6B the single layer of oxide semiconductor material 611 issandwiched between and is in contact with non-ohmic metal 613 andohmic-metal 612. In FIG. 6A the non-ohmic metal 613 is shared with thememory element 302. In FIG. 6B, the non-ohmic metal 613 is in contactwith a metal layer 615 such that a metal/oxide semiconductor/metalstructure is positioned on top of the memory element 302. In FIG. 6C andFIG. 6D the single layer of oxide semiconductor material 611 is incontact with and is sandwiched between and ohmic metal (623, 633) andnon-ohmic metal (622, 632). In FIG. 6C, the ohmic metal 623 is incontact with a metal layer 615 such that a metal/oxidesemiconductor/metal structure is positioned on top of the memory element302. In FIG. 6D, the ohmic metal 633 is shared with the memory element302. The memory element 302 may be positioned at the bottom of the stackfor memory cell 300 as depicted or may be positioned at the top of thestack for the memory cell 300 (not shown).

Suitable materials for the oxide semiconductor 611 include but are notlimited to perovskites and binary oxides. The perovskite can be a dopedSrTiO₃ (e.g., doped with niobium Nb or lanthanum La), for example. Thebinary oxide can be nickel oxide NiO_(x), zinc oxide ZnO_(x), or tinoxide SnO_(x), for example. Suitable non-ohmic metals include but arenot limited to platinum Pt, palladium Pd, and iridium Ir. Suitable ohmicmetals include but are not limited to magnesium Mg, indium In, aluminumAl, and tantalum Ta. Suitable materials for the metal 615 include butare not limited to platinum Pt, iridium Ir, and iridium oxide IrO_(x).In some applications the ohmic metal may not be necessary if the oxidesemiconductor 611 includes a graded doping profile with a very highdoping profile at the ohmic interface, that is, the doping concentrationis highest at the ohmic interface.

The NOD 621 can be fabricated using processing steps including but notlimited to metal deposition, CMP to produce metal plugs, oxidesemiconductor 611 deposition, graded-doping of the oxide semiconductor611 during deposition or post deposition using implantation, patterningand etching the oxide semiconductor 611, annealing for contactimprovement, and deposition of additional layers of material, such asglue layers, for example.

The memory element 302 can be comprised of discrete layers of material(e.g., etched layers in the stack for memory cell 300) or can becontinuous and un-etched layers of material that include one or morelayers of a conductive metal oxide (CMO) that are in contact with eachother and are continuous and un-etched layers and a continuous andun-etched electronically insulating layer (e.g., yttria-stabilizedzirconia—YSZ) in contact with an uppermost of the CMO layers. Portionsof the one or more layers of CMO that are positioned in the stack formemory cell 300 can be electrically conductive and portions outside ofthe stack can be made electrically nonconductive insulating metal oxides(IMO's) by treating those portions to transform them from conductive toinsulating (e.g., by ion implantation). If ion implantation is used totransform portions of the CMO to an IMO, portions of the memory stack(e.g., an electrode, a hard mask layer, or the NOD 321 or 621) can beused as an implantation mask operative to shield the portion of the CMOlayer that is to remain electrically conductive from the ions duringimplantation such that the portions of the CMO layer positioned outsidethe memory stack are bombarded by the ions and are transformed intoIMO's.

FIG. 7A depicts an example of arrayed memory cells according to variousembodiments of the invention. In this example, a memory cell 300includes a memory element 302 and NOD 321 positioned above or below (notshown) the memory element 302. The memory element 302 can include theabove mentioned CMO layer(s) and electronically insulating layer denotedas 710 and 712 respectively. The layers 710 and 712 can be discretelayers as depicted or they can be continuous and un-etched layers (notshown) as described above. Memory cell 300 further includes terminals771 and 773. Terminals 771 and 773 can be electrically coupled with orcan be formed as electrodes 774 and 778. The electrodes (774, 778) canbe made from an electrically conductive material including, but notlimited to, platinum (Pt), gold (Au), silver (Ag), iridium (Ir), iridiumoxide (IrO_(x)), ruthenium (Ru), palladium (Pd), aluminum (Al), alloysof those materials, and the like. The electrodes (774, 778) can be incontact with and/or electrically coupled with conductive array linesoperative to apply the aforementioned voltages for data operations, suchas read voltages and write voltages (e.g., program and erase voltages)across one or more selected memory cells 300. The memory element 302 andNOD 321 are electrically in series with each other and electrically inseries with the electrodes (774, 778).

Memory cell 300 can be formed between conductive array lines, such asarray lines 312 and 310. Thus, memory cell 300 can be formed in an arrayof other memory cells 300. In FIG. 7A, array lines 312′ and 310′ aredepicted in heavy line to illustrate that those array lines havevoltages for data operations applied to them such that memory cell 300′is the selected memory cell for the data operation. The array can be thecross-point array 350 including groups of conductive array lines 310 and312. For example, array lines 310 can be electrically coupled with theelectrodes 774 of the memory cells 300 and/or may be in contact with asurface 772 s of the electrodes 774, and array lines 312 can beelectrically coupled with the electrodes 778 of the memory cells 300and/or may be in contact with a surface 778 s of the electrodes 778.Although not depicted in FIG. 7A, the active circuitry that applies thevoltages for data operations is positioned below the array 350 on asubstrate with the array 350 fabricated directly on top of the substrateand the array 350 in contact with the substrate.

FIG. 7B depicts an integrated circuit including memory cells disposed ina single layer or in multiple layers of memory, according to variousembodiments of the invention. In this example, integrated circuit 780 isshown to include either multiple layers 750 of memory (e.g., layers 752a, 752 b, 752 n) or a single memory layer 751 (e.g., layer 752) formedon a base layer 754. As will be described in greater detail below, thelayers 754 and 752 a, 752 b, 752 n or layers 754 and 752 are notphysically separate layers as depicted in FIG. 7B for purposes ofillustration, rather they are different portions of a unitary die 800(not shown) comprised of a FEOL portion for the base layer 754 and aBEOL portion for the layer 752 or layers 752 a, 752 b, 752 n. In atleast some embodiments, each layer (e.g., layer 752 or layers 752 a, 752b, 752 n) of memory can be a cross-point memory array 350 includingconductive array lines 310 and 312 arranged in different directions toaccess re-writable memory cells 300 such as two-terminal memory cells asdescribed above. Examples of conductive array lines include X-lineconductive array lines (e.g., 310) and Y-line conductive array lines(e.g., 312). The X and Y conductive array lines are sometimes referredto as row lines and column lines respectively. Base layer 754 caninclude a bulk semiconductor substrate (e.g., a silicon wafer) uponwhich memory access circuits 753 for performing data operations on thememory cells 300 in memory 750 or 751 are fabricated. Base layer 754 mayinclude other circuitry that may or may not be related to dataoperations on memory. Base layer 754 and circuitry 753 (e.g., CMOSactive circuitry such as decoders, drivers, sense amps, buffer,registers, etc.) can be formed in a front-end-of-the-line (FEOL)fabrication process and multiple memory layers 750 or single memorylayer 751 can be formed in a back-end-of-the-line (BEOL) fabricationprocess tailored to fabricating layer(s) of memory arrays on top of thebase layer 754. Although not depicted, the base layer 754 can include aninter-level interconnect structure configured to include nodes (e.g.,openings in a dielectric material or electrically conductive structuressuch as vias, plugs, thrus, damascene structures, etc.) for facilitatingelectrical coupling between the circuitry 753 and the conductive arraylines (310, 312) of the array(s) so that signals (e.g., read and writevoltages) for data operations (e.g., read and write operations) areelectrically communicated between the array(s) and the circuitry 753.The inter-level interconnect structure can be one of the lastmicroelectronic structures fabricated during the FEOL processing.

Moving on to FIG. 7C, where a vertically stacked array 790 includes aplurality of memory layers A, B, C, and D with each memory layerincluding memory cells 300 a, 300 b, 300 c, and 300 d. Although onlyfour layers are depicted, the array 790 can include fewer layers or caninclude additional layers up to an nth layer. The array 790 includesthree levels of x-direction conductive array lines 710 a, 710 b, and 710c, and two levels of y-direction conductive array lines 712 a, and 712b. Unlike the configuration for array 350 in FIG. 7A, the memory cells300 a, 300 b, 300 c, and 300 d depicted in FIG. 7C share conductivearray lines with other memory cells that are positioned above, below, orboth above and below that memory cell. The conductive array lines, thememory cells, dielectric materials that electrically isolate structuresin the array 790 (not shown), and other structures in the array 790 areformed BEOL above the base layer 754 (not shown) as indicated by +Z onthe Z-axis above the dashed line at origin 0; whereas, the activecircuitry for performing data operations on the array 790 and theinterconnect structure for electrically coupling the active circuitrywith the array 790 (e.g., the conductive array lines) are previouslyformed FEOL as indicated by −Z on the Z-axis below the dashed line atorigin 0. Accordingly, the BEOL structure for array 790 is formed on topof the FEOL structure for base layer 754 with the order of fabricationgoing in a direction from −Z (i.e., FEOL) to +Z (i.e., BEOL) along theZ-axis.

Reference is now made to FIG. 8A, where integrated circuit 780 includesthe base layer 754 and active circuitry 753 fabricated on the base layer754 (e.g., a silicon Si wafer). The integrated circuit 780 is comprisedof a single unitary die 800 having a first portion (i.e., the base layer754) fabricated first using FEOL processing and a second portion (i.e.,the single memory layer 752) fabricated second and formed directly ontop of the base layer 754 using BEOL processing, such that the secondportion is integrally formed with the first portion and completes theformation of the die 800. As one example, the base layer 754 can be asilicon (Si) wafer and the active circuitry 753 can be microelectronicdevices formed on the base layer 754 using a CMOS fabrication process.The memory cells 300 and their respective conductive array lines (310,312) can be fabricated on top of the active circuitry 754 in the baselayer 754. Those skilled in the art will appreciate that an inter-levelinterconnect structure (not shown) can electrically couple theconductive array lines (310, 312) with the active circuitry 753 whichmay include several metal layers. For example, vias can be used toelectrically couple the conductive array lines (310, 312) with theactive circuitry 753. The active circuitry 753 may include but is notlimited to address decoders, sense amps, memory controllers, databuffers, direct memory access (DMA) circuits, voltage sources forgenerating the read and write voltages, just to name a few. Activecircuits 810-818 can be configured to apply the select voltagepotentials (e.g., read and write voltage potentials) to selectedconductive array lines (310′, 312′). Moreover, the active circuitry 753may be electrically coupled with the conductive array lines (310′, 312′)to sense a read current I_(R) that flows through selected memory cells300′ during a read operation and the read current I_(R) can be sensedand processed by the active circuitry 753 to determine the conductivityprofiles (e.g., the resistive state) of the selected memory cells 300′.Examples of conductivity profiles include but are not limited to aprogrammed conductivity profile written to a memory cell 300′ during aprogramming data operation and an erased conductivity profile written toa memory cell 300′ during an erase data operation. Memory cells 300 canstore data as a plurality of conductivity profiles that can include theprogrammed or erased conductivity profiles only (e.g., only 1-Bit ofdata stored per memory cell 300) or more than two conductivity profilesfor storing multiple bits of data per memory cell 300 (e.g., two or morebits of data per memory cell 300). The direction of current flow for theread current I_(R) will depend on a magnitude and polarity of a readvoltage applied across terminals 304 and 306. In some applications, itmay be desirable to prevent un-selected array lines (310, 312) fromfloating. The active circuits 753 can be configured to apply anun-select voltage potential (e.g., approximately a ground potential) tothe un-selected array lines (310, 312). A dielectric material 811 (e.g.,SiO₂) may be used where necessary to provide electrical insulationbetween elements of the integrated circuit 780.

Moving now to FIG. 8B, an integrated circuit 780 includes a plurality ofnon-volatile memory arrays that are vertically stacked above one another(e.g., along a +Z axis) and are positioned above the base layer 754 thatincludes the active circuitry 753. The integrated circuit 780 includesvertically stacked memory layers A and B and may include additionalmemory layers up to an nth memory layer. The memory layers A, B, . . .through the nth layer can be electrically coupled with the activecircuitry 753 in the base layer 754 by an inter-level interconnectstructure as was described above. Layer A includes memory cells 300 aand first and second conductive array lines (310 a, 312 a), Layer Bincludes memory cells 300 b and first and second conductive array lines(310 b, 312 b), and if the nth layer is implemented, then the nth layerincludes memory cells 300 n and first and second conductive array lines(310 n, 312 n). Dielectric materials 825 a, 825 b, and 825 n (e.g.,SiO₂) may be used where necessary to provide electrical insulationbetween elements of the integrated circuit 820. Active circuits 840-857can be configured to apply the select voltage potentials (e.g., read andwrite voltage potentials) to selected conductive array lines (e.g., 310a, b, n, and 312 a, b, n). Driver circuits 850 and 857 are activated toselect conductive array lines 310′ and 312′ to select memory cell 300 b′for a data operation. As was described above, the active circuits 753can be used to sense the read current I_(R) (not shown) from selectedmemory cells 300 b′ during a read operation and can be configured toapply the un-select voltage potential to the un-selected array lines. Asdescribed above, the integrated circuit 780 comprises the die 800 thatis a unitary whole comprised of a FEOL circuitry portion fabricated onbase layer 754 and a BEOL memory portion having multiple memory layersthat is in contact with the FEOL portion and is fabricated directly ontop of the FEOL portion.

In FIG. 8C, an integrated circuit 780 includes base layer 754, activecircuitry 753, and vertically staked memory layers A, B, C, and D thatare fabricated above the base layer 754. Active circuits 840-857 areconfigured to perform data operations on the vertically staked memorylayers A, B, C, and D. Driver circuits 844 and 857 are activated toselect memory cell 300 a′ for a data operation and driver circuits 842and 848 are activated to select memory cell 600 d′ for a data operation.A dielectric layer 851 is operative to electrically isolate the variouscomponents of integrated circuit 780. As described above, the integratedcircuit 780 comprises the die 800 that is a unitary whole comprised of aFEOL circuitry portion fabricated on base layer 754 and a BEOL memoryportion having multiple memory layers that is in contact with the FEOLportion and is fabricated directly on top of the FEOL portion.

Moving on to FIG. 9, an exemplary memory system 900 includes theaforementioned non-volatile two-terminal cross-point memory array 350(array 350 hereinafter) and the plurality of first conductive and secondconductive traces denoted as 310 and 312, respectively. The memorysystem 900 also includes an address unit 903 and a sense unit 905. Theaddress unit 903 receives an address ADDR, decodes the address, andbased on the address, selects at least one of the plurality of firstconductive traces (denoted as 310′) and one of the plurality of secondconductive traces (denoted as 312′). The address unit 903 applies selectvoltage potentials (e.g., read or write voltages) to the selected firstand second conductive traces 310′ and 312′. The address unit 903 alsoapplies a non-select voltage potential to unselected traces 310 and 312.The sense unit 905 senses one or more currents flowing through one ormore of the conductive traces. During a read operation to the array 350,current sensed by the sense unit 905 is indicative of stored data in amemory cell 300′ positioned at an intersection of the selected first andsecond conductive traces 310′ and 312′. A bus 921 coupled with anaddress bus 923 can be used to communicate the address ADDR to theaddress unit 903. The sense unit 905 processes the one or more currentsand at least one additional signal to generate a data signal DOUT thatis indicative of the stored data in the memory cell. In someembodiments, the sense unit 905 may sense current flowing through aplurality of memory cells and processes those currents along withadditional signals to generate a data signal DOUT for each of theplurality of memory cells. A bus 927 communicates the data signal DOUTto a data bus 929. During a write operation to the array 350, theaddress unit 903 receives write data DIN to be written to a memory cellspecified by the address ADDR. A bus 925 communicates the write data DINfrom the data bus 929 to the address unit 903. The address unit 903determines a magnitude and polarity of the select voltage potentials tobe applied to the selected first and second conductive traces 310′ and312′ based on the value of the write data DIN. For example, onemagnitude and polarity can be used to write a logic “0” and a secondmagnitude and polarity can be used to write a logic “1”. In otherembodiments, the memory system 900 can include dedicated circuitry thatis separate from the address unit 903 to generate the select potentialsand to determine the magnitude and polarity of the select potentials.

One skilled in the art will appreciate that the memory system 900 andits components (e.g., 903 and 905) can be electrically coupled with andcontrolled by an external system or device (e.g., a microprocessor or amemory controller). Optionally, the memory system 900 can include atleast one control unit 907 operative to coordinate and control operationof the address and sense units 903 and 905 and any other circuitrynecessary for data operations (e.g., read and write operations) to thearray 350. Although only one array 350 is depicted, the array 350 cancomprise a single layer of memory (e.g., 752) or multiple layers ofvertically stacked memory (752 a, 752 b, 752 n) as depicted in FIGS.7A-8C. One or more signal lines 909 and 911 can electrically couple thecontrol unit 907 with the address and sense units 903 and 905. Thecontrol unit 907 can be electrically coupled with an external system(e.g., a microprocessor or a memory controller) through one or moresignal lines 913.

As was described above in reference to FIGS. 7A through 8C, one or moreof the arrays 350 can be positioned over a substrate 754 that includesactive circuitry 753 and the active circuitry 753 can be electricallycoupled with the array(s) 350 using an interconnect structure thatcouples signals from the active circuitry 753 with the conductive arraylines 310 and 312. In FIG. 9, the busses, signal lines, control signals,the address, sense, and control units 903, 905, and 907 can comprise theactive circuitry 753 and its related interconnect, and can be fabricatedon the substrate 754 (e.g., a silicon wafer) using a microelectronicsfabrication technology, such as CMOS, for example.

Reference is now made to FIG. 10, where an electrical system 1000includes a CPU 1001 that is electrically coupled 1004 with a bus 1002,an I/O unit 1007 that is electrically coupled 1010 with the bus 1002,and a storage unit 1005 that is electrically coupled 1008 with the bus1002. The I/O unit 1007 is electrically coupled 1012 to external sources(not shown) of input data and output data. The CPU 1001 can be any typeof processing unit including but not limited to a microprocessor (μP), amicro-controller (μC), and a digital signal processor (DSP), forexample. Via the bus 1002, the CPU 1001, and optionally the I/O unit1007, performs data operations (e.g., reading and writing data) on thestorage unit 1005. The storage unit 1005 stores at least a portion ofthe data in the aforementioned non-volatile two-terminal cross-pointarray as depicted in FIGS. 5 through 8C. Each memory array includes aplurality of the two-terminal memory cells 300. The configuration of thestorage unit 1005 will be application specific. Example configurationsinclude but are not limited to one or more single layer non-volatiletwo-terminal cross-point arrays (e.g., 752) and one or more verticallystacked non-volatile two-terminal cross-point arrays (e.g., 752 a-752n). In the electrical system 1000, data stored in the storage unit 1005is retained in the absence of electrical power. The CPU 1001 may includea memory controller (not shown) for controlling data operations to thestorage unit 1005.

Alternatively, the electrical system 1000 may include the CPU 1001 andthe I/O unit 1007 coupled with the bus 1002, and a memory unit 1003 thatis directly coupled 1006 with the CPU 1001. The memory unit 1003 isconfigured to serve some or all of the memory needs of the CPU 1001. TheCPU 1001, and optionally the I/O unit 1007, executes data operations(e.g., reading and writing data) to the non-volatile memory unit 1003.The memory unit 1003 stores at least a portion of the data in theaforementioned non-volatile two-terminal cross-point array as depictedin FIGS. 7A through 8C. Each memory array can include a plurality of thetwo-terminal memory cells 300 with each memory cell 300 including thetwo-terminal memory element 302 and the Schottky diode NOD (321, 621).The configuration of the memory unit 1003 will be application specific.Example configurations include but are not limited to one or more singlelayer non-volatile two-terminal cross-point arrays (e.g., 752) and oneor more vertically stacked non-volatile two-terminal cross-point arrays(e.g., 752 a-752 n). In the electrical system 1000, data stored in thememory unit 1003 is retained in the absence of electrical power. Dataand program instructions for use by the CPU 1001 may be stored in thememory unit 1003. The CPU 1001 may include a memory controller (notshown) for controlling data operations to the non-volatile memory unit1003. The memory controller may be configured for direct memory access(DMA).

Reference is now made to FIG. 11, where a top plan view depicts a singlewafer (denoted as 1170 and 1170′) at two different stages offabrication: FEOL processing on the wafer denoted as 1170 during theFEOL stage of processing where active circuitry 753 is formed; followedby BEOL processing on the same wafer denoted as 1170′ during the BEOLstage of processing where one or more layers of non-volatile memory areformed. Wafer 1170 includes a plurality of the base layer die 754 (seeFIGS. 7B-8C) formed individually on wafer 1170 as part of the FEOLprocess. As part of the FEOL processing, the base layer die 754 may betested 1172 to determine their electrical characteristics,functionality, performance grading, etc. After all FEOL processes havebeen completed, the wafer 1170 is optionally transported 1104 forsubsequent BEOL processing (e.g., adding one or more layers of memorysuch as single layer 752 or multiple layers 752 a, 752 b, 752 n)directly on top of each base layer die 754. A base layer die 754 isdepicted in cross-sectional view along a dashed line FF-FF where thesubstrate the die 754 is fabricated on (e.g., a silicon Si wafer) andits associated active circuitry are positioned along the −Z axis. Forexample, the one or more layers of memory are grown directly on top ofan upper surface 754 s of each base layer die 754 as part of thesubsequent BEOL processing.

During BEOL processing the wafer 1170 is denoted as wafer 1170′, whichis the same wafer subjected to additional processing to fabricate thememory layer(s) directly on top of the base layer die 754. Base layerdie 754 that failed testing may be identified either visually (e.g., bymarking) or electronically (e.g., in a file, database, email, etc.) andcommunicated to the BEOL fabricator and/or fabrication facility.Similarly, performance graded base layer die 754 (e.g., graded as tofrequency of operation) may identified and communicated to BEOL thefabricator and/or fabrication facility. In some applications the FEOLand BEOL processing can be done by the same fabricator or performed atthe same fabrication facility. Accordingly, the transport 1104 may notbe necessary and the wafer 1170 can continue to be processed as thewafer 1170′. The BEOL process forms the aforementioned memory layer(s)directly on top of the base layer die 754 to form a finished die 800that includes the FEOL circuitry portion 754 along the −Z axis and theBEOL memory portion along the +Z axis (see FIGS. 7B-8C). Across-sectional view along a dashed line BB-BB depicts a memory devicedie 800 with a single layer of memory 752 grown directly on top of basedie 754 along the +Z axis, and alternatively, another memory device die800 with three vertically stacked layers of memory 752 a, 752 b, and 752c grown directly on top of base die 754 along the +Z. Finished die 800on wafer 1170′ may be tested 1174 and good and/or bad die identified.Subsequently, the wafer 1170′ can be singulated 1178 to remove die 800(e.g., die 800 are precision cut or sawed from wafer 1170′) to formindividual memory device die 800. The singulated die 800 maysubsequently be packaged 1179 to form integrated circuits 1190 formounting to a PC board or the like, as a component in an electricalsystem (not shown). Here a package 1181 can include an interconnectstructure 1187 (e.g., pins, solder balls, or solder bumps) and the die800 mounted in the package 1181 and electrically coupled 1183 with theinterconnect structure 1187 (e.g., using wire bonding). The integratedcircuits 1190 may undergo additional testing 1185 to ensurefunctionality and yield.

In general, the devices and methods discussed herein are applicable tosemiconductor memory (i.e., material used for data storage) formed andfabricated using various types of materials such as silicon dioxide,silicon oxide, noble metals, conductive metal oxides (e.g.,perovskites), and others. Examples of such memories include SRAM, MRAMand FLASH memories, cross-point array (layout) memory and stackedcross-point array memory (e.g., whether single layer non-volatiletwo-terminal cross-point arrays, or one or more vertically stackednon-volatile two terminal cross arrays), three/third-dimension memoryarrays (including those that emulate other types of memory, providingmemory combinations within a single component), resistive state memorydevices, and memory systems.

The foregoing examples have been described in some detail for purposesof clarity of understanding, but are not limited to the detailsprovided. There are many alternative ways and techniques forimplementation. The disclosed examples are illustrative and notrestrictive.

What is claimed is:
 1. A memory device, comprising: a re-writeablenon-volatile memory element (ME) having exactly two terminals andincluding electrically in series with the two terminals a binaryconductive oxide layer including mobile ions and, a tunnel barrier layerhaving a thickness less than approximately 50 Angstroms; and a selectiondevice including a layer of metal in contact with a single layer ofdoped polycrystalline silicon, the contact operative to form a singleSchottky diode, the Schottky diode and the ME are electrically in serieswith each other.
 2. The memory device of claim 1, wherein the singlelayer of doped polycrystalline silicon is doped n−.
 3. The memory deviceof claim 1, wherein the single layer of doped polycrystalline siliconincludes a first portion that is doped n− and a second portion that isdoped n+, the first portion is in contact with the layer of metal andthe second portion is not in contact with the layer of metal.
 4. Thememory device of claim 3 and further comprising: an electricallyconductive silicide layer in contact with the second portion.
 5. Thememory device of claim 4, wherein the silicide layer comprises a nickelsilicide or a cobalt silicide.
 6. The memory device of claim 1, whereinthe metal layer comprises a metal selected from the group consisting oftungsten, aluminum, and platinum.
 7. The memory device of claim 1,wherein one of the layers of the selection device is in direct contactwith one of the layers of the ME.
 8. The memory device of claim 1,wherein one of the two terminals is electrically coupled with a firstconductive array line and another one of the two terminals iselectrically coupled with a second conductive array line.
 9. The memorydevice of claim 8, wherein the first conductive array line comprises oneof a plurality of first conductive array lines and the second conductivearray line comprises one of a plurality of second conductive array linesand the plurality of first and second conductive array lines aredisposed in a cross-point array.
 10. The memory device of claim 9,wherein the cross-point array is positioned above, is in contact with,and is fabricated back-end-of-the-line (BEOL) directly above asemiconductor substrate including active circuitry fabricatedfront-end-of-the-line (FEOL) on the semiconductor substrate andelectrically coupled with the plurality of first and second conductivearray lines.
 11. The memory device of claim 10 and further comprising: aplurality of the cross-point arrays in contact with one another andvertically disposed over one another in a stacked configuration.
 12. Thetwo-terminal memory cell of claim 1, wherein the ME and the selectiondevice are positioned above and are fabricated back-end-of-the-line(BEOL) directly above a semiconductor substrate including activecircuitry fabricated front-end-of-the-line (FEOL) on the semiconductorsubstrate and electrically coupled with the first and second terminals.13. The two-terminal memory cell of claim 1, wherein the ME isconfigured to store at least one-bit of non-volatile data as a pluralityof conductivity profiles that can be non-destructively determined byapplying a read voltage across its two terminals, the data is retainedin an absence of electrical power, and the data can be reversiblyswitched between a programmed conductivity profile and an erasedconductivity profile by applying a write voltage across the twoterminals.
 14. The two-terminal memory cell of claim 13, wherein theselection device is configured to substantially block current flowthrough the ME for voltages other than the read voltage or the writevoltage.
 15. A memory device, comprising: a re-writeable non-volatilememory element (ME) having exactly two terminals and includingelectrically in series with the two terminals a binary conductive oxidelayer including mobile ions and, a tunnel barrier layer having athickness less than approximately 50 Angstroms; and a selection deviceconfigured as a single Schottky diode including a single layer of anoxide semiconductor material, an ohmic metal in contact with the oxidesemiconductor material, and a non-ohmic metal in contact with the oxidesemiconductor material, the selection device and the ME are electricallyin series with each other.
 16. A two-terminal memory cell, comprising: are-writeable non-volatile memory element (ME) having exactly twoterminals and including electrically in series with the two terminals abinary conductive oxide layer including mobile ions and, a tunnelbarrier layer having a thickness less than approximately 50 Angstroms;and a selection device configured as a single Schottky diode including asingle layer of an oxide semiconductor material in contact with anon-ohmic metal, the oxide semiconductor material including a gradeddoping profile having a doping concentration that is highest at aninterface between the oxide semiconductor material and the non-ohmicmetal, and the selection device and the ME are electrically in serieswith each other.